1. Field of the Invention
The present invention relates to a data processing apparatus and method for controlling access to memory.
2. Description of the Prior Art
As data processing tasks increase in complexity, it is becoming more common for data processing systems to include more than one processing unit to handle the performance of these tasks or processes. In particular, in addition to main processing logic, for example a central processing unit (CPU), it is often the case that a number of additional pieces of special purpose hardware logic are provided for performing particular tasks. Examples of such additional pieces of hardware are hardware accelerators such as those used to perform certain video processing functions, digital signal processors (DSPs), etc.
To enable such additional hardware logic to undertake certain tasks on behalf of the main processing logic, it is clear that those additional hardware units must be given access to the required data sets that need processing. Currently, this is done by arranging the main processing unit to share a certain portion of memory with the relevant additional hardware logic units, and typically this is achieved by reserving a pool of contiguous, physically addressed memory at boot-up time. However, as the data sets to be processed increase in size, the likelihood of providing more additional special purpose hardware units such as accelerators increases, but certain hardware units may be used only infrequently and hence it becomes undesirable to reserve the large amount of memory required for such processes that a user of the system may only use relatively infrequently. For example, VGA H.264 requires 3 Mbytes for a picture buffer, and a 5 Megapixel camera requires 15 Mbytes for an RGB processed image.
With this in mind, it is becoming impractical to reserve a pool of contiguous, physically addressed memory at boot-up time for the sharing of data between the main processing logic and the additional processing logic, and accordingly this has driven the need to share memory from the operating system managed dynamic memory pool. As such memory is typically virtually addressed, this requires management of the virtual to physical address translation process to ensure that the correct data is accessed by the additional hardware when performing a task on behalf of the main processing logic.
With regard to the portion of memory to be shared, the complex operating systems that exist today generally make very poor use of static on-chip memory, and applications which wish to take advantage of this memory must be specifically linked and managed to do so. This hence makes static on-chip memory a poor candidate for use as the memory to be shared between the main processing logic and the additional hardware logic units for the earlier-described purposes. One possible alternative approach is to consider developing a level of cache which could be shared between the main processing logic and any other required hardware logic, but typical systems often have multiple levels of caches, and such an approach would give rise to some cache coherency issues that would need addressing. For example, it needs to be ensured that both the main processing logic and the additional hardware logic see the same data when they make a particular access.
Additionally, in multi-processing systems, system level security issues can arise if data is to be shared between various pieces of processing logic. For example, the main processing logic may be arranged to handle both secure/trusted data and non-secure/non-trusted data. If certain tasks are to be delegated to an additional piece of hardware logic, then it is possible that some trusted data will need to be shared, whilst other trusted data will be private to the particular processor. This means that in such situations any simple bus master aware decoding techniques used to police accesses to memory to ensure that non-secure processes do not access secure data, will be too limiting, and accordingly in such situations it would be necessary to provide techniques which would enable access to the trusted data to be correctly policed.
Accordingly, it would be desirable to provide a technique which enables memory to be shared between the main processing logic and one or more additional pieces of processing logic to enable certain tasks to be delegated to the additional processing logic on behalf of the main processing logic, but which alleviates the concerns outlined above.